Field of the Invention
The present invention relates to a crystal oscillation circuit which is low in current consumption and stably short in oscillation start time.
Background Art
As a crystal oscillation circuit used in an electronic timepiece or the like, there has been known such a configuration as shown in Patent Document 1. FIG. 5 is illustrated in a range not departing from the crystal oscillation circuit shown in Patent Document 1.
The crystal oscillation circuit 109 is comprised of PMOS transistors P31 and P32, NMOS transistors N31 and N32, capacitors C1, C2, C3 and C4, a feedback resistor 29, a constant current source 49, a constant voltage circuit 19, and a crystal vibrator 69.
An oscillation inverter configured by the PMOS transistor P31 and the NMOS transistor N31 is controlled by a current I9 which allows an operating current to flow through the constant current source 49. Thus, the crystal oscillation circuit is capable of reducing current consumption by reducing the current I9. Further, an amplitude limiter circuit comprised of the PMOS transistor P32 and the NMOS transistor N32 is capable of reducing current consumption of the crystal oscillation circuit by limiting the amplitude of a terminal XOUT. Furthermore, it is possible to reduce the current consumption of the crystal oscillation circuit by driving the crystal oscillation circuit by a constant voltage VREG outputted from the constant voltage circuit 19. Besides, the crystal oscillation circuit has also an effect in that an oscillation start time is made quick by the amplitude limiter circuit.
[Patent Document 1] Japanese Patent Application Laid-Open No. 2011-134347